职位介绍
摘自雇主发布的职位信息 · Arrow Electronics, Inc. · 发布于2026年10月1日
At-least 6 years of experience in System Verilog HVL and C++/C At-least 6 year of experience in UVM. Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, …